The present invention relates to a deglitch switch for switching between two clocks, and more particularly, for generating a clock for a hard disk drive read/write channel.
As general background, when writing to a disk drive, an external clock source, such as quartz crystal is used to generate a clock for timing information. When the data is read back from the disk drive, the clock must be synchronized with the data itself, and thus a phase-locked loop is used to recover the clock from the data which is read back from the disk. In read/write channel, different clocks are used at different portions of the coding/decoding operation, and there is a need to switch from one clock to the other.
When switching between clocks, it is desirable to avoid short pulses, or glitches. A traditional method for eliminating such a glitch is shown in FIG. 1. The two clocks which are being switched, clock A and clock B, are provided to a first multiplexer 12. The output of multiplexer 12 is provided to a dynamic latch 14, which is in turn provided to a second multiplexer 16. A controller circuit 18 controls the operation of the multiplexers and the dynamic latch in response to a select signal on a select line 20. The controller selects between the two clock inputs via a first multiplexer select line 22. The controller receives the output clock of multiplexer 12 on a line 24, and uses it to time the selecting of the dynamic latch on a control line 26 and a selection through a second multiplexer 16 on a line 28. Such a system is used, for example, in chips made by SGS Thompson. The outputs of multiplexer 12 may have a glitch. The glitch is blocked by the dynamic latch. The controller waits until a good clock arrives, then turns on the latch, and the deglitched clock goes through. The second multiplexer 16 is used for power down control. Its function is not deglitch related.
As can be seen, the clock input signals must progress through two multiplexers and a dynamic latch. This long path results in a corresponding long delay. The circuit of FIG. 1 also uses dynamic latches both in the clock path, and in the controller 18. In a power down or other situations, the dynamic latch (which includes capacitive memory) may lose this memory and thus give a wrong clock signal. Accordingly, there is a need to reset it and power up. Finally, the circuit of FIG. 1 has the drawback of being difficult to debug because of wrong states it can go into where it will never self-correct, except on a power on and reset. This design controls the clock selection only at the transistor period of the control signal. In case a wrong clock is selected, (due to, say, noise, or clock hang-up, or the dynamic latch losing memory due to leakage, etc.), the wrong clock signal would stay selected. This situation is like an edge triggered dynamic D-flip-flop. Once the triggering edge is over, the input signal loses control of the output. The circuit then needs a power on reset, or mode switching signal to correct it.